1. Field of the Invention
The present invention relates to remote automatic testers used in dynamic testing of integrated circuits and, in particular, to driver circuits for use in such testers.
2. The Prior Art
The dynamic operating characteristics of an integrated circuit (IC), such as switching speed and propagation delay time, are typically determined using an automatic tester. For example, the tester may be programmed to transmit a sequence of test signals to various input or input/output (I/O) ports of a device under test (DUT), such as an IC, and to measure the resulting output levels and response times of the DUT. Such testing may determine whether the DUT functions properly and also determine the required timing characteristics of the circuitry that will be connected to the input, output, and I/O ports of the DUT after the testing process is complete.
Since the tester must generate DUT input signals and measure the output response signals of the DUT to accuracies approaching plus-or-minus 100 picoseconds, the tester must be constructed so that it will not distort the waveforms of the output signals of the DUT, or at least so that it will distort these waveforms only in ways that are predictable and repeatable.
Each DUT output signal must pass through a transmission line which connects the DUT port to a comparator within the tester. This transmission line should be terminated in its characteristic impedance (Z.sub.0) if the DUT is capable of driving such a load, or by a "Z-clamp" circuit as described below.
Each I/O port of the DUT must also be connected to a driver circuit within the tester. To minimize the load that the tester applies to the DUT output, the driver and comparator are generally connected to the DUT via a single transmission line. This method of connection requires that the driver be located at the end of the transmission line, very close to the termination circuitry. Any physical separation between the driver and the termination circuitry can cause timing errors in two ways. First, the driver's output signal path can include a transmission line stub which introduces reflections and distorts the driver's output waveform. Second, the output capacitance of the turned-off driver can distort the output waveform of the DUT by causing reflections in the DUT output-signal path.
A typical prior-art driver exhibits the following problems:
1. It requires a separate circuit for terminating or clamping the transmission line between itself and the DUT. This terminator or clamp must necessarily be some finite distance from the driver, resulting in a transmission line stub.
2. It does not have an adequate "turned-off" state, so that when the DUT attempts to drive the driver's output high or low, the driver will produce an output current that tends to make the transition slower.
3. When driving to a digital "high" level, it does not adequately sink the current that impinges on it as a result of transmission line reflections that try to drive its output to a more positive level.
4. When driving to a digital "low" level, it does not adequately sink the current that impinges on it as a result of transmission line reflections that try to drive its output to a more negative level.
Improperly terminated transmission lines in the test environment can cause significant time-measurement errors, especially when CMOS devices being tested generate narrow pulses. As the clock speed of digital CMOS devices increases to 100 MHz and beyond, the problem of I/O errors caused by transmission line aberrations on the device interconnections becomes much more severe.
End-users typically eliminate this problem by packaging the devices in multi-chip modules to reduce the interconnection distances. However, transmission line aberrations are not easily eliminated in the test environment, since the physical separation between the device under test (DUT) and the tester's driver and comparator circuits is usually an order of magnitude greater than the minimum interconnection distances in a multi-chip module. Inappropriate termination of transmission lines in a test system significantly detracts from the timing and voltage accuracy specifications of the tester's comparator performance.
Clamping Techniques. Known techniques for terminating the transmission lines in a test system include the "hard clamp", the "Z-clamp", source-terminating the lines in their characteristic impedance (Z.sub.0), terminating the tester ends of the lines in their characteristic impedance, and the programmable load.
A further technique, suggested by Barber (M. R. BARBER, Subnanosecond timing measurements on MOS devices using modern VLSI test systems, INTERNATIONAL TEST CONFERENCE, 1983) and others, is to place the tester's comparators very close to the DUT. This has the significant advantage of minimizing differences between the test environment and the end-use environment. A significant disadvantage is that, in order to handle DUT I/O pins, the tester's drivers would also have to be placed very close to the DUT. To date, no one has built such a system in a cost-effective manner.
If the output impedance of the DUT is less than the characteristic impedance of the transmission line, and if the tester end of the transmission line is left open, then the voltage transitions seen by the comparator in the tester are different from the voltage transitions generated by the DUT. A single edge generated by the DUT is observed to overshoot and then ring. Subsequent edges are observed as being superimposed on the ringing caused by previous edges. Timing errors occur if the DUT output edges are not separated by several times the propagation delay of the transmission line. Even invalid-data errors can occur if the DUT output edge rate is high enough.
However, most existing CMOS output drivers are not designed to drive a terminated transmission line. Thus, alternate approaches must be used in the test setup to minimize transmission line ringing and the resulting timing (and possibly data) errors.
The "Hard Clamp". This circuit consists of two Schottky diodes and two voltage sources. One diode is connected between the input and the positive clamp voltage; the other diode is connected between the input and the negative clamp voltage. The magnitudes of the clamp voltages are typically adjusted to be equal to (or a few hundred millivolts less than) the magnitudes of the expected output voltages of the DUT, so that the DUT normally drives a small amount of current into the clamp at its maximum and minimum excursions. When a DUT with a source impedance of less than 50 ohms drives this circuit, the waveform at the end of the transmission line tends to overshoot. The overshoot is "shorted out" by one of the clamp diodes. Since the transmission line is terminated by a circuit whose dynamic impedance is less than Z.sub.0, a reflection which propagates back to the DUT supplies more energy to the transmission line. This cycle repeats for several times the round-trip delay of the transmission line until the current in the transmission line falls to a negligible value. If the DUT output produces another edge during this time, the comparator in the tester sees the edge superimposed on the ringing. Although the output waveforms observed at the comparator "look good," the timing of the edges seen by the comparator do not correspond exactly to the timing of the edges produced by the DUT.
The "Z-Clamp". U.S. patent application Ser. No. 08/037,507 of Kenneth R. Wilsher entitled "Method and Circuit for Controlling Voltage Reflections on Transmission Lines" (continuation of Ser. No. 07/764,026, filed Sep. 23, 1991) describes alternate transmission line termination clamp circuits. As discussed in the Wilsher patent application, the impedance characteristics of FIG. 1 are approximated with Z-clamp circuits such as shown in FIGS. 2A and 2B. These circuits are similar to the hard clamp, except that a resistor is placed in series with the diodes so that the impedance is equal to 50 ohms when the diodes are conducting. An advantage of this impedance characteristic is that the dynamic impedance of the termination circuit is equal to Z.sub.0. Therefore, the current in the transmission line caused by a DUT output transition falls to zero at twice the round-trip delay time of the transmission line (2*T.sub.d) after the DUT output transition.
The timing errors of the Z-clamp are similar to those of the hard clamp for pulse widths less than twice the propagation time T.sub.d Of the transmission line. For pulse widths greater than 2*T.sub.d, the Z-clamp causes negligible timing error, since the current in the transmission line caused by the first edge has dropped to zero by the time the second edge occurs.
When the DUT is an ECL or a GTL circuit or any circuit that is designed to drive into a terminated transmission line, it is ideal to terminate the transmission line between the DUT and its associated comparator within the tester by connecting a fixed resistor with a value of Z.sub.0 between the end of the transmission line and a low impedance voltage source that is set to the appropriate voltage. If the actual circuit that is connected to the end of the transmission line has an equivalent circuit that is different from this ideal, reflections and therefore timing measurement errors will occur.
The clamp circuits proposed in Wilsher's U.S. patent application Ser. No. 08/037,507 do not address the condition described in the previous paragraph. The circuits shown in FIGS. 2A and 2B (corresponding to FIGS. 5A and 5B of Wilsher's application) would serve adequately if Wilsher's voltage (V.sub.cc -V.sub.d) were reprogrammed to (V.sub.t -V.sub.d) and if Wilsher's voltage V.sub.d were reprogrammed to (V.sub.t +V.sub.d), where V.sub.t is the termination voltage and V.sub.d is the diode-junction voltage drop. However, voltages (V.sub.t -V.sub.d) and (V.sub.t +V.sub.d) would have to be carefully controlled and coordinated with the actual value of V.sub.d at the prevailing temperature, to prevent excess current from flowing from the node at voltage (V.sub.t +V.sub.d) through diodes D1 and D2 to the node at (V.sub.t -V.sub.d).
Source-Terminating the Transmission Line. This can be accomplished by either of two methods, assuming that the transmission lines in the tester have a characteristic impedance of 50 ohms, which appears to be a de facto standard. One method is to design the DUT output drivers to have a source impedance of 50 ohms when driving either high or low. The other method is to design the DUT output drivers to have the same impedance when driving either high or low, but less than 50 ohms. In the latter case, a resistor must be added to the test fixture near the DUT so that the total impedance driving the transmission line will be equal to 50 ohms.
Terminating the Tester End of Transmission Line in its Characteristic Impedance. This technique will always produce ideal waveshapes at the tester's comparators. The amplitude of these waveforms will be attenuated: EQU V.sub.out =V.sub.s *Z.sub.0 /(Z.sub.s +Z.sub.0),
where V.sub.s is the voltage and Z.sub.s is the impedance of the DUT's output driver. This attenuation must be considered when calculating the comparison voltages if the device outputs are not terminated in the end-use application.
A disadvantage of this technique is that most existing CMOS output drivers are not designed to drive a terminated transmission line. However, the philosophy of designing high-speed output drivers that cannot drive a terminated transmission line must be questioned. If a device is going to be tested, then it must operate satisfactorily in its test environment(s) as well as in its end-use environment. If a DUT with output impedance Z.sub.s drives an unterminated 50 ohm transmission line in the test environment of length T.sub.d and the DUT switches between voltages V.sub.oh and V.sub.ol, then the DUT's output must supply a current equal to (V.sub.oh -V.sub.ol)/(Z.sub.s +50) for a period of time equal to 2*T.sub.d. If the same transmission line is terminated at (V.sub.oh +V.sub.ol)/2, then the maximum output current is reduced by 50%. Terminating the tester's transmission line in its characteristic impedance will therefore reduce ground-bounce in the DUT, and even reduce power dissipation at some output frequencies.
The Programmable Load. This circuit has been used since the earliest days of IC testing, when DTL and TTL devices comprised a significant part of the IC market. It was designed to test the outputs of devices that drive DTL and TTL inputs. Such inputs draw DC current from their driving sources. A programmable load typically consists of a Schottky diode bridge, switchable current sources, resistors, and a termination voltage source. When the input signal from the DUT is more negative than the termination voltage, a specified current (I.sub.ol) is drawn from the DUT by the load. Similarly, a differently specified current (I.sub.oh) is driven into the DUT from the load whenever the input signal is more positive than the termination voltage. A programmable load is typically used in conjunction with a hard clamp or Z-clamp.
A programmable load compromises the timing accuracy of the tester. The input capacitance of the programmable load reduces the apparent bandwidth of the DUT output signal as observed at the comparator input. And, if a programmable load is "on", the bridge and its current sources look like a "diode+capacitor" load at the end of the transmission line. The diodes are forward-biased whenever the DUT output is at the same state for a significant period of time, but they are reverse-biased by the first edge emanating from the DUT. Subsequent edges that occur soon after the first edge will not drive the same capacitive load as the first edge. The fact that the load changes from edge to edge causes an uncalibratable timing error. The maximum error depends on the stray capacitance of the bridge (i.e., the capacitances of the diodes, current sources, current switches, and the board or module on which they are mounted).
Whether all or some or very little of this error affects the time measurement of a specific edge depends on the time between the edge being measured and the previous edge, the decay time of the bridge's stray capacitance (i.e., the capacitance times the voltage change divided by the programmed current (I.sub.oh or I.sub.ol)), and the calibration technique (i.e., whether the system calibration is based on the first edge or a later edge). Moreover, the maximum programmable load current may not be sufficient to provide adequate termination for the input signal.
If a CMOS IC produces output transitions which are separated in time by less than twice the delay of the transmission lines in its tester environment (2*T.sub.d), then good timing accuracy can be achieved only by terminating these transmission lines in their characteristic impedance. This can be achieved either by designing the drive impedance of the IC outputs to be equal to Z.sub.0, or by placing resistive terminations near the tester's comparators. Either approach places significant requirements on the IC design. If a CMOS IC produces output transitions that are separated in time by more than 2*T.sub.d and less than 4*T.sub.d (or even less than 6*T.sub.d), then a significant advantage in timing accuracy can be achieved by using a Z-clamp instead of a hard clamp. A programmable load should not be used when testing high-speed devices.